Field of the Invention
The invention relates to a buffer memory configuration, which is disposed between a data transmitter and a data receiver for the purpose of data communication, which is connected to the transmitter and the receiver via signal lines, which includes at least one memory for data buffering, and which has a memory management unit that controls reading from and writing to the memory via an address/data bus.
Buffer memories of this type are generally known as first-in, first-out memories (FIFO). The implementation of such a FIFO is described, for example, in Electronic Circuits: Design and Applications, U. Tietze and Ch. Schenk, Springer-Verlag, Berlin 1991, pp. 254-262.
A FIFO is a special form of a shift register. The common feature of such a shift register is that the data appear at the output in the same order as they were entered at the input: the first word read in (first-in) is thus read out first (first-out) as well. In contrast to a shift register, however, this operation can take place fully synchronously in a FIFO, i.e., the read-out clock is decoupled from the read-in clock.
In modern FIFOs, the data are no longer shifted, rather input and output addresses are specified in a memory module by means of two pointers, the so-called write pointer and the read pointer. In that case, the write pointer points to the first free address, while the read pointer points to the last address occupied. The pointers are usually realized by simple counters. The memory module is typically a random access memory (RAM).
A further FIFO of the generic type is described in German Published, Non-Proscuted Patent Application DE 44 33 692 A1. FIG. 1 of that application shows such a FIFO, in which a sector of a memory area, which may be arranged in a random access memory (RAM), for example, is mapped. The addressed memory area in this case comprised addresses 22, 23, . . . 31. In FIG. 1A, the data words D1-D4 are written to the memory locations having the addresses 24, 25, 26 and 27. The read pointer RP points to the memory location having the address 24 and the write pointer WP to the memory location having the address 28.
If two further data words are then intended to be written to the queue (D5 and D6), then the data word D5 is written to the memory location having the address 28 and the data word D6 to the memory location having the address 29 (FIG. 1B). The write pointer WP is incremented by the number of written words. If data are then intended to be read from the memory locations, then reference is made via the read pointer RP to the memory location having the address 24 and the data word D1 is read out.
After the reading operation (FIG. 1C) the read pointer RP points to the memory location having the address 25 and the write pointer WP points to the memory location having the address 30 after the write operation. After the write and read operations, the new data content of the queue comprises the data words D2-D6. The data words are buffer-stored in successive memory locations.
The disadvantage of such memory processing of a buffer memory is that memory locations in the buffer memory which have just been written to can only be read after the memory locations of the buffer memory which were written to chronologically before the memory location have been read. This is disadvantageous particularly when, in the buffer memory, only the data content of a few memory locations ever changes but the data content of the remaining memory locations mainly remains the same. Such a buffer memory architecture is thus very inflexible and the read-out is thus extremely time-consuming.
The following problem also frequently arises: the data transmitter, for example the bus, is inactive. If the bus is activated, then very large data packets must be written all at once to the buffer memory in a very short time. The data receiver, for example the central processing unit, however, frequently has a very much higher clock frequency than the data transmitter and, consequently, can read data from the buffer memory very much more rapidly than the data transmitter can write data thereto. As a result, the performance of the buffer memory is limited by the size of the buffer memory and the capability of the data transmitter to write data packets to the buffer memory as fast as they are read by the data receiver.
However, a FIFO buffer memory architecture according to the prior art only ever allows a data packet which maximally corresponds to the size of the buffer memory to be read by the data transmitter before the buffer memory can be written to again by the data transmitter. This processing procedure is very slow and, moreover, drastically limits the performance of the entire system.
In order to increase the performance of a buffer memory, therefore, it is necessary to provide a very large memory module (RAM) as buffer memory which can completely hold the volume of data to be transferred. This is exceedingly cost-intensive, however, particularly in the case of a microprocessor.
In the case of the data packets which are transmitted directly in succession by the data transmitter, it is frequently the case that only a few individual items of data change while the remaining data remain the same. This is the case, for example, with a data mask, a data form or the like. However, in a buffer memory of the generic type, the total volume of data is always written to the memory and then also read out again in its entirety. This is exceedingly complicated and takes a very long time as well.
Furthermore, with the existing FIFO memory architecture it is not possible simultaneously to write data to the memory and read data from the memory.
It is accordingly an object of the invention to provide a buffer memory configuration, which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type and which is characterized by a more flexible, powerful buffer memory architecture.
With the foregoing and other objects in view there is provided, in accordance with the invention, a buffer memory configuration, comprising:
a data transmitter, a data receiver, and a buffer memory connected for data communication signal lines between the data transmitter and the data receiver;
the buffer memory including a memory for data buffering, an address/data bus connected to the memory, and a memory management unit controlling reading from and writing to the memory via the address/data bus;
the memory being mappable onto an address space exactly half as large as the memory, a first half of the memory defining a first memory page and a second half of the memory defining a second memory page, each address in the address space being assigned a respective memory location on each of the memory pages; and
the memory management unit generating a significant bit assigning in each case the two memory locations having the same address to the address space of the first memory page and to the address space of the second memory page.
In accordance with an added feature of the invention, the data transmitter and the data receiver are a respective one of a bus with a multiplicity of bus lines and a central processing unit, each of the bus and the central processing unit being operable as the data transmitter and the data receiver.
In accordance with an additional feature of the invention, the memory has at least one end point, each the end point being assigned a base address and an end address, and each the end point being adapted to occupy either memory locations of the first memory page or memory locations of the second memory page or memory locations of the first and second memory pages with the same addresses.
In accordance with another feature of the invention, the end points are adapted to store therein at least one data packet each having at least a data size of an individual memory location.
In accordance with a further feature of the invention, an end address of an end point is defined by a maximum data packet size transmitted by the data transmitter.
The buffer memory configuration according to the invention makes it possible to use a standard memory, which is typically designed as a simple RAM, to achieve a processing procedure of data writing and reading operations which has a much higher performance than compared with the prior art. It is advantageous that, compared with the prior art, this necessitates a much smaller memory than would be required by the maximum incoming volume of data.
Typically, however, data transmitter and data receiver are not necessarily designed as central processing unit and as USB bus. The central processing unit and the USB bus may in this case function alternately both as data transmitter and data receiver.
In accordance with again an additional feature of the invention, the memory management unit includes at least one of the following elements:
a first address generator for generating the addresses of the first memory page;
a first read/write pointer for reading data from and writing data to memory locations of the first memory page;
a second address generator for generating the addresses of the second memory page;
a second read/write pointer for reading data from and writing data to memory locations of the second memory page;
a SWAP unit for controlling a change-over between the first and second memory pages.
In accordance with again an added feature of the invention, at least one register device is provided for storing the base addresses of the end points.
In accordance with again another feature of the invention, at least one of the data transmitter and the data receiver generate a direction bit defining a direction of the data transfer.
In accordance with again a further feature of the invention, the memory management unit is adapted to identify whether an end point is empty or full.
In accordance with yet an added feature of the invention, the end points of a given memory page are writeable to and readable from individually and in any order, independently of a content of remaining end points of the given memory page.
In accordance with yet an additional feature of the invention, each address within the address space of an end point can be set selectively for writing thereto and for reading therefrom.
In accordance with yet another feature of the invention, a further unit is connected to the bus via further signal lines, the further unit being another central processing unit, a coprocessor, and/or at least one peripheral unit.
In accordance with yet a further feature of the invention, a synchronization device synchronizes the clock signals of the data transmitter and of the data receiver with one another.
With the above and other objects in view there is also provided, in accordance with the invention, a method of operating the above-described buffer memory configuration. The method comprises defining a given configuration wherein:
each end point having exclusively memory locations of the first memory page is writeable to by the data transmitter;
the SWAP unit switches an assignment of written-to end points based on the significant bit from the data transmitter to the data receiver; and
the end points whose assignment has been changed with regard to the significant bit are readable by the data receiver.
In the alternative, or additionally, further configuration may be defined, wherein:
each end point having exclusively memory locations of both memory pages with respectively identical addresses is simultaneously writeable to by the data transmitter and readable from by the data receiver;
the SWAP unit switches the assignment of the recently written-to end point based on the significant bit from the data transmitter to the data receiver; and
the end points are again writeable to by the data transmitter and readable from by the data receiver.
Accordingly, the buffer memory configuration may be selectively operated in the given configuration, in the further configuration, or in the given and the further configuration.
In other words, the buffer memory configuration according to the invention affords the possibility that, simultaneously, data can be written to the memory by the data transmitter and data can be read from the memory by the data receiver. In this way, the flexibility of the buffer memory architecture is also enhanced.
Furthermore, it is possible to write to and read from individual end points, which may comprise a plurality of memory locations, for example, in a targeted manner without the data content of the remaining end points changing. It is advantageous that the data content of the remaining end points need not then also be read out. In this way it is possible to channelize and structure the data transfer. Moreover, data to be transmitted can be transmitted very rapidly in this way.
The invention is particularly advantageous if data are to be transmitted in the form of a data mask, a form or the like in which only individual items of data ever change. These respectively changing items of data can then be forwarded very rapidly.
The individual end points can be operated both in the so-called single buffer mode and in the dual buffer mode. In a very advantageous application, one portion of the end points is operated in the single buffer mode, while the other portion of the end points is operated in the dual buffer mode.
The invention is particularly advantageous in a so-called USB module. The bus is then a USB bus. However, the bus can also connect a further processor, a coprocessor or at least one peripheral to the buffer memory configuration.
A further favorable application of the buffer memory configuration is in a microprocessor, a microcomputer or in a communications network.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in buffer memory configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.